Complementary Metal-Oxide-Semiconductor (CMOS) is the primary technology for ultra large-scale integrated (ULSI) circuits. These ULSI circuits combine both P-channel Metal-Oxide-Semiconductor (PMOS) devices and N-channel Metal-Oxide-Semiconductor (NMOS) devices on the same integrated circuit.
To gain performance advantages, scaling down the size of CMOS devices has been the principal focus of the microelectronics industry over the last two decades. Unfortunately, it has not been possible to obtain maximum performance advantage of scaling because both the NMOS and PMOS devices can not be individually optimized.
In the past, the conventional process involved doping a silicon substrate and growing a gate oxide on the substrate followed by a deposition of polysilicon. A photolithographic process was used to etch the polysilicon to form the device gate. This could be followed by a polysilicon reoxidation or not depending on the process. As device sizes were scaled down, the source and drain junctions had to scale down. As the source and drain junctions are scaled down, series resistance increases, which degrades the device performance. To reduce series resistance, advanced CMOS devices have to have junction structures that include relatively deep source and drain junctions to improve series resistance and very shallow source and drain extension junctions to permit the scale down. The difficulties of controlling the displacements of these structures become apparent from the following process described below which is used after the formation of the polysilicon gate.
For a "single spacer" process, an N-type dopant would be implanted to form the shallow source/drain extension junctions of the n-channel devices followed by a P-type dopant to form the deep source/drain extension junctions of the p-channel devices. The single oxide or oxynitride spacers then would be formed. With the N-type dopant source/drain extension junctions protected by the single spacers, the N-type dopant would be more deeply implanted to in the n-channel device region to form the deep source/drain junctions. There would then be a first rapid thermal anneal (RTA) for the N-type dopant source/drain junctions. With the P-type dopant source/drain extension junctions also protected by the single spacer, the P-type dopant would be more deeply implanted to in the p-channel device region to form the deep source/drain junctions. There would then be a second rapid thermal anneal (RTA) for the P-type dopant source/drain junctions.
For a "double spacer" process, an N-type dopant would be implanted to form the shallow source/drain extension junctions of the n-channel devices. The first spacer would then be formed. With the N-type dopant source/drain extension junctions protected by the first spacer, the N-type dopant would be more deeply implanted to in the n-channel device region to form the deep source/drain junctions. There would then be a first RTA for the N-type dopant source/drain junctions. The first RTA is followed by a P-type dopant to form the shallow source/drain extension junctions of the p-channel devices. The second spacer then would be formed. With the P-type dopant source/drain extension junctions protected by the first and second spacers, the P-type dopant would be more deeply implanted to in the p-channel device region to form the deep source/drain junctions. There would then be a second RTA for the P-type dopant source/drain junctions.
In the single spacer process, both types of devices can not be optimized because the P-type source/drain extension junction implantations are followed by the first and second RTA's. The transient enhanced diffusion caused by the two RTA's inherently increases the displacement of the shallow P-type source/drain extension junctions and degrades the performance of the p-channel devices.
In the double spacer process, both types of devices can not be optimized because the first spacer controls the displacements of both the deep N-type dopant source/drain junctions and the shallow P-type dopant source/drain extension junctions.
It has long been known that the inability to optimize devices would lead to detrimental compromises in performance so optimization process improvements have been long sought but have eluded those skilled in the art. Similarly, it has long been known that the problems would become more severe with the reductions in device size to deep sub-micron levels.